1. Field of the Invention
The present invention relates in general to switched-capacitor circuitry and methods and in particular to switched-capacitor circuits and methods with improved settling time and systems using the same.
2. Description of the Related Art
Switched-capacitor circuits are used in a wide range of applications, including analog-to-digital converters (ADCs), digital-to-analog converters (DACs) delta-sigma modulators, filters, power supplies, and voltage regulators. Generally, switched capacitor techniques allow for the construction of accurate, compact, frequency tunable circuits without the use of resistors. This is particularly advantageous in integrated circuit designs, where the construction of precise resistor-based circuits is difficult and unnecessarily consumes chip area.
In the basic switched-capacitor integrator, an input voltage is sampled onto a sampling capacitor during a first clock phase. During a second (non-overlapping) clock phase, the charge on the sampling capacitor is transferred to the integrator capacitors. The output of the integrator is fedback to the summing node with a integrator capacitor. The impedance of the circuit depends on the size of the sampling and integrator capacitors and the frequency of the clock.
One of the key performance parameters in switched-capacitor circuits is the settling time. In particular, it is important that the circuit output ramp to its final value quickly and smoothly. This is particularly true in high performance applications, such as audio analog-to-digital and digital-to-analog conversion circuits where discontinuities in the circuit response can affect the ultimate quality of the audio signal presented to the listener.
According to one such embodiment, a switched capacitor circuit is disclosed which includes an operational amplifier having an input and an output, a sampling capacitor and a set of switches. During a first phase, a set of switches samples an input voltage by charging sampling capacitor. During a first portion of a second phase, the operational amplifier input is electrically coupled to sampling capacitor with a first path having a first time constant. During a second portion of the second phase, the operational amplifier input is electrically coupled with the sampling capacitor through a second path having a second time constant, the second time constant being smaller than the first time constant.
The present inventive principles substantially reduce the settling time when a switched capacitor techniques are being practiced. Specifically, circuits and methods are disclosed which substantially reduce the negative output spikes in switched capacitor circuits by controlling the rate of voltage change at the switch capacitor circuit summing nodes. In particular, multiple sets of switches are provided for transferring charge to the summing node. One set of switches has a large time constant such that the voltage change is relatively slow and a second set of switches has a smaller time constant such that the change in voltage at the summing node is relatively rapid.